In the production process of semiconductor integrated circuit devices, after a great number of integrated circuits are formed on a wafer composed of, for example, silicon, a probe test that basic electrical properties of each of these integrated circuits are inspected, thereby sorting out defective integrated circuits is generally conducted. This wafer is then diced, thereby forming semiconductor chips. Such semiconductor chips are housed and sealed in respective proper packages. Each of the packaged semiconductor integrated circuit devices is further subjected to a burn-in test that electrical properties thereof are inspected under a high-temperature environment, thereby sorting out semiconductor integrated circuit devices having latent defects.
In the probe test conducted for integrated circuits formed on a wafer, a method that a wafer is divided into a plurality of areas, in each of which, a plurality of, for example, 16 integrated circuits have been formed, a probe test is performed collectively on all the integrated circuits formed in an area, and the probe test is successively performed collectively on the integrated circuits formed in other areas has heretofore been adopted. In recent years, there has been a demand for collectively performing the probe test on a greater number of integrated circuits for the purpose of improving inspection efficiency and reducing inspection cost.
In the burn-in test on the other hand, it takes a long time to individually conduct electrical inspection of a great number of integrated circuit devices because each integrated circuit device that is an object of inspection is fine, and its handling is inconvenient, whereby inspection cost becomes considerably high. From such reasons, in recent years, there has been proposed a WLBI (Wafer Level Burn-in) test in which the burn-in test is performed collectively on a great number of integrated circuits formed on a wafer.
In such electrical inspection of integrated circuits, such as probe test or burn-in test, a probe card having a great number of contacts arranged in accordance with a pattern corresponding to a pattern of electrodes to be inspected in a wafer, which is an object of inspection, is in use for electrically connecting each of the electrodes to be inspected to a tester.
As the probe card, those, the contact member of which is of a cantilever type or vertical needle type, have heretofore been widely known. Flat type probe cards, the contact member of which is equipped with an anisotropically conductive connector having an anisotropically conductive film, and a sheet-like probe obtained by arranging electrode structures in an insulating sheet, have been recently proposed (see Patent Art. 1). These probe cards are so constructed that such a contact member as described above is arranged on a circuit board for inspection composed of, for example, a multi-layer printed wiring board.
When electrical inspection is performed collectively on a great number of integrated circuits formed on a wafer, a circuit board for inspection composed of a multi-layer printed wiring board, the number of layers is considerably great, for example, 30 to 40 layers or more, is used as a circuit board for inspection making up a probe card used in such inspection.
However, it is difficult to surely produce a multi-layer printed wiring board, the number of layers is considerably great, and which has high connection reliability. Thus, the yield of the circuit board for inspection becomes considerably low, so that a problem that the production cost of the probe card is increased, and in turn the inspection cost is increased arises.    Patent Art. 1: Japanese Patent Application Laid-Open No. 2004-53409.